1. Field of the Invention
The present invention relates to a capacitor array and a method for manufacturing the same. In particular, the present invention relates to a capacitor array including an outer terminal electrode, at least a portion of which includes a plating film directly connected to an internal electrode, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, along with miniaturization of portable electronic apparatuses, e.g., cellular phones and portable music players, high density mounting of electronic components on wiring substrates incorporated in the electronic apparatuses have been rapidly advanced. In response to this, an electronic component, in which a plurality of circuit elements are incorporated into one chip, is desired in order to reduce the mounting space and the number of components required to be mounted. For example, various array type electronic components, such as a capacitor array, for example, have been developed.
Multi-terminal type electronic components, such as array type electronic components, usually include substantially rectangular component main bodies, and a plurality of substantially band-shaped outer terminal electrodes that are disposed on individual side surfaces of the component main bodies. There are technical issues that, as described below, arise during the formation of the above-described substantially band-shaped outer terminal electrodes.
(1) The outer terminal electrodes are formed so as to cover the ends of the internal electrodes exposed at the side surfaces of the component main bodies in order to prevent reduced reliability.
(2) The outer terminal electrodes are formed so as to ensure that desired distances between adjacent outer terminal electrodes in order to prevent the occurrence of a solder bridge during mounting.
The substantially band-shaped outer terminal electrodes have been formed primarily by baking electrically conductive pastes. With this method, the precision of the application of the electrically conductive paste is limited. Therefore, the electrically conductive paste is typically applied so as to have a width slightly greater than the exposure width of the internal electrode such that a predetermined distance between the outer terminal electrodes is ensured. Consequently, the amount of miniaturization of a multi-terminal type electronic component has been limited when conventional methods, such as baking of the electrically conductive paste, have been used to form the substantially band-shaped outer terminal electrode.
A method capable of overcoming the above-described problems is disclosed in Japanese Unexamined Patent Application Publication No. 2004-327983, which discloses a method in which an outer terminal electrode is formed by direct plating instead of baking an electrically conductive paste. Japanese Unexamined Patent Application Publication No. 2004-327983 describes that it is possible to selectively deposit a metal on an end edge of an exposed internal electrode by applying direct plating, and, therefore, the outer terminal electrode having substantially the same width as the exposure width of the internal electrode can be formed with a high degree of precision.
Japanese Unexamined Patent Application Publication No. 2004-327983 describes that the outer terminal electrode is formed primarily by electroless plating. However, with the electroless plating, there are problems in that a plating film formation rate is relatively low and the density of the resulting plating film is relatively low. In order to improve the plating film formation rate and the density of the resulting plating film, a method has been used in which a catalyst substance, e.g., Pd, is formed prior to the formation of the plating film. When this method is used, problems occur in that the process is complicated and the cost is increased.
Furthermore, the electroless plating utilizes the principle that film formation is conducted by a chemical reaction in a plating solution. Therefore, a plating film is likely to be deposit at undesired locations, and a plating film may grow in a width direction, that is, toward adjacent outer terminal electrodes. In this case, the distance between outer terminal electrodes may be reduced to the extent that a solder bridge is produced during mounting.
Moreover, Japanese Unexamined Patent Application Publication No. 2004-327983 describes that in order to facilitate formation of a continuous plating film between exposed portions of a plurality of internal electrodes, dummy internal electrodes referred to as “anchor tabs” are formed between adjacent internal electrodes, and ends of the dummy internal electrodes are exposed between adjacent internal electrodes. Particularly, a first dummy internal electrode and a second dummy internal electrode are disposed on the same planes as those of mutually opposed first internal electrode and second internal electrode, respectively. The first dummy internal electrode and the second dummy internal electrode are electrically insulated from the first internal electrode and the second internal electrode, respectively. The first dummy internal electrode is exposed at a side surface at which the second internal electrode is exposed, and the second dummy internal electrode is exposed at a side surface at which the first internal electrode is exposed.
However, when such dummy internal electrodes are provided, the exposure area of the internal electrodes increases by the area of the dummy internal electrodes. Consequently, problems may occur in that a degree of sealing between the dielectric layers is reduced and the reliability of multi-terminal type electronic components deteriorates.